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CADENCE TECHNOLOGY CAN DELIVER INCREASED COMPUTER PERFORMANCE By Al Marsh

"It also delivers increased productivity, usability, and accuracy necessary for spice-accurate comprehensive full-chip power grid analysis on our most advanced designs, including accurate modeling of transistors, mixed-signal and analog blocks." Shoji Ichino, Technology Development Division, General Manager at Fujitsu Microelectronics, Ltd. is referring to technology advances by the Cadence Encounter Power System providing in the design phase a comprehensive view of timing and power integrity:

• full-chip power grid analysis

• enhanced static and dynamic analysis

• electromigration (example videos)

• thermal analysis

• Statistical analyses for on-chip power impacts due to package and board parasitics.

High performance in today's computers requires keeping the pipeline fed. Obstacles to achieving this are unpredictable programming branches and slowly reacting storage resulting in between ten and twenty cycles, between five and ten on average. Conditional execution to avoid branches is restricted to a limited set of useful instructions. As stages of pipelines are extended more precise branch prediction units are needed.

High performance is further restricted by non-local storage access delays. Requests processed through layers of cache make the pipeline incrementally wait five to ten cycles. Outside of cache, depending on ease of address translation, the delay may be as low as 100 - 300 cycles. If fault conditions occur, processing can be stalled for tens of millions of cycles. Therefore, management of cache needs to be executed quickly. In addition, use of Parallelism in the code provides opportunity for performance enhancement by the processor.

About the author:  Al Marsh is President and CEO of ALCO.com Company @ alcocom.com.....a Delaware USA Corporation providing Engineering Consultants, Distributors of HIRO™ Beverages  (NEW! HIRO™ Energy), SeaAloe and other dietary supplements among venues "Providing Balance To Lifestyles For Business".

Advanced Memory Optimization Techniques for Low-Power Embedded Processors by Manish Verma and Peter Marwedel (Hardcover - May 8, 2007)

The design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the memory wall problem. Therefore, this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses.----Editorial Review

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